Implementation of an 8-bit Low-power Multiplier based on Reversible Gate Technology

Reversible logic has attracted tremendous interest among the researchers in low power VLSI field due to their simple structure and improved energy efficiency. In this paper, the implementation of an 8-bit low power multiplier based on reversible gate technology is reported. The structure of the reversible gate multiplier consists of following components: the first part is the reversible partial product generator circuit (PPGC) which will be realized by reversible AND gate; the second part is constructed by several TSG gates whose function is to add the carryout of the previous level and PPCG of current level together. In the second part, some XNOR gates and NOR gates with improved designs to save power and speed up the performance are presented. The 8-bit reversible gate multiplier is designed and simulated in PSPICE. PSPICE simulation verifies the correct function of the multiplier. In order for comparison, an 8-bit static CMOS multiplier is also designed. PSPICE power simulation is used to simulate the power consumption of both reversible gate multiplier and the static CMOS multiplier for the same given input pattern sequence. Simulation results show that reversible gate multiplier leads to effective power saving compared to static CMOS multiplier. Keywords— Reversible logic, Reversible gate, Low power VLSI, Low power CMOS design.